60 Second Timer
"In this design problem, you will have the opportunity to draw together all of the concepts and skills that you have developed pertaining to the topic of asynchronous counter design" (Problem 3.2.4 Sixty Second Timer)
Problem Statement-Design, simulate, and build a 60 second timer
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Constraints-Timer will have two inputs, one being the clock, the other the reset
-Use SSI logic for the tens place -Use MSI logicfor the ones place -Has to be able to count to 60 and stop -Entire circuit resets at 0 |
DocumentationThe first step of the design process, the 60 second timer was first sketched out in the notebook:
The 60 Second Timer built and simulated, on the computer, using Multisim (CDS):
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CalculationsThe sketch was derived from the logic which follows MSI (left) and SSI (right) inputs and outputs:
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Final Design
This 60 second timer was a bit of a challenge to make, taking into account the fact that we had to build an asynchronous timer, using two separate types of logic. Very simply, if you have an asynchronous counter circuit design (as we do here), the every flip-flop input will depend upon the previous flip-flop’s output. In this way, the 60 second timer circuit design is an asynchronous counter. What this design is able to is count from 0-60, and stop at 60. Whenever the only SPDT switch, on the circuit, is logic 0, then the count resets, and stays at 00. In addition, if the counter is counting, at the SPDT switch suddenly turned to
logic 0, even if it was in the middle of the count, the whole design resets and stays at 00.
The way I approached designing of the 60 second timer, was by taking the circuit apart, and splitting it into two components: the MSI part and the SSI part of the design. My first step was to design a counter using MSI logic (which would be the one’s place) which would count up from 0-9, and then reset. The outputs of the MSI logic (which come from the 74LS93): A, B, C, and D all go through an encoder, which is then inverted, and as the outputs go through 220Ω resistors, they serve as the inputs for the Common Cathode 7-segment display, which will be wired to ground (this display will serve for the ones place in the counter). To clarify,
the snapshot of the Multisim simulation uses a Common Anode 7-segment display, which is why inverters are missing, and the display being wired up to 5V. The MSI part of the 60 second time will count to 9 and then reset to 0 because when the count reaches 10 (or 1010 in binary), that count will go through a 4-input NAND gate (output A and C will go through inverters first since they are 0’s whenever the count is 10) which will turn out combined inputs of 1, into a 0 and since input will go through a 2-input NAND gate with the SPDS switch (at high logic, or 1), the combined inputs will yield 1&0, turning into a 0 and since it is a NAND gate, it will ultimately be a 1 for the R02 input on the 74LS93. Whenever R01 (which is wired to 5V so it’s always 1) and R02 are both ones, this will make the whole MSI circuit reset to 0.
What you are going to want to do for the SSI part of the counter is first build a divided-by-two circuit using D Flip-Flops (74LS74).
You are going to want the count to go up to 6 (since this will be the display for the tens place) so the number of flip-flops used will be three. You simply find this out by taking the number of desired flip-flops and raising two to that number of flip-flops power. We have three flip-flops, so 2^3 equal 8 counts (0-7) which is exactly what you need. In this part of the process, you are tempted to want to reset the count, so that whenever the count reaches 6 it will go back to 0 (which in a way is what you want to happen) at least that is what I understood the goal to be. I had to go through a lot of trial and error in order for me to see that whenever the SPDT switch is to 0, then the whole SSI part of the 60 second counter resets to 0. You do not necessarily need a reset of 6, because you want the count to stop at 6, not reset at 6. After figuring that out, making the two separate 7-segment displays count in a decimal fashion was easy. Every time the MSI output resets to 0, you want to go up 1 in the tens place (19, 20 or 39, 40). You simply take the 4-input NAND gate output and run it through an inverter (since it will be a 0), turning it into a 1, and making the SSI design start counting.
At this point the circuit that I had was one in where all of the criteria were met, except for one: how to make the count from both MSI and SSI displays stop at 60. All you do is simply take the 110 binary output from the SSI logic (outputs C and B), which is equivalent to 6 in decimal, and run it through a 2-input NAND gate, so whenever the outputs C and B are 1’s, they will be turned into a 0. Know you take this output and connect it to a 2-input AND gate, in which the other input will be the Clock, and the output will be wired to INA on the 74LS93, making it so that whenever the count reaches 60, the counts stop, but do not reset. This was truly a culmination of both Asynchronous Counters and MSI Counters knowledge, and was a great learning experience, in that you actually had to come up with your own design, with the given constraints.
logic 0, even if it was in the middle of the count, the whole design resets and stays at 00.
The way I approached designing of the 60 second timer, was by taking the circuit apart, and splitting it into two components: the MSI part and the SSI part of the design. My first step was to design a counter using MSI logic (which would be the one’s place) which would count up from 0-9, and then reset. The outputs of the MSI logic (which come from the 74LS93): A, B, C, and D all go through an encoder, which is then inverted, and as the outputs go through 220Ω resistors, they serve as the inputs for the Common Cathode 7-segment display, which will be wired to ground (this display will serve for the ones place in the counter). To clarify,
the snapshot of the Multisim simulation uses a Common Anode 7-segment display, which is why inverters are missing, and the display being wired up to 5V. The MSI part of the 60 second time will count to 9 and then reset to 0 because when the count reaches 10 (or 1010 in binary), that count will go through a 4-input NAND gate (output A and C will go through inverters first since they are 0’s whenever the count is 10) which will turn out combined inputs of 1, into a 0 and since input will go through a 2-input NAND gate with the SPDS switch (at high logic, or 1), the combined inputs will yield 1&0, turning into a 0 and since it is a NAND gate, it will ultimately be a 1 for the R02 input on the 74LS93. Whenever R01 (which is wired to 5V so it’s always 1) and R02 are both ones, this will make the whole MSI circuit reset to 0.
What you are going to want to do for the SSI part of the counter is first build a divided-by-two circuit using D Flip-Flops (74LS74).
You are going to want the count to go up to 6 (since this will be the display for the tens place) so the number of flip-flops used will be three. You simply find this out by taking the number of desired flip-flops and raising two to that number of flip-flops power. We have three flip-flops, so 2^3 equal 8 counts (0-7) which is exactly what you need. In this part of the process, you are tempted to want to reset the count, so that whenever the count reaches 6 it will go back to 0 (which in a way is what you want to happen) at least that is what I understood the goal to be. I had to go through a lot of trial and error in order for me to see that whenever the SPDT switch is to 0, then the whole SSI part of the 60 second counter resets to 0. You do not necessarily need a reset of 6, because you want the count to stop at 6, not reset at 6. After figuring that out, making the two separate 7-segment displays count in a decimal fashion was easy. Every time the MSI output resets to 0, you want to go up 1 in the tens place (19, 20 or 39, 40). You simply take the 4-input NAND gate output and run it through an inverter (since it will be a 0), turning it into a 1, and making the SSI design start counting.
At this point the circuit that I had was one in where all of the criteria were met, except for one: how to make the count from both MSI and SSI displays stop at 60. All you do is simply take the 110 binary output from the SSI logic (outputs C and B), which is equivalent to 6 in decimal, and run it through a 2-input NAND gate, so whenever the outputs C and B are 1’s, they will be turned into a 0. Know you take this output and connect it to a 2-input AND gate, in which the other input will be the Clock, and the output will be wired to INA on the 74LS93, making it so that whenever the count reaches 60, the counts stop, but do not reset. This was truly a culmination of both Asynchronous Counters and MSI Counters knowledge, and was a great learning experience, in that you actually had to come up with your own design, with the given constraints.